Codigo Compuertas
-- Este es un Codigo que se desarrollo en la Pagina de EdaPlayground para verificar el funcionamiento de las compuertas
-- Codigo de Diseño
library IEEE;
use IEEE.std_logic_1164.all;
entity Compuertas_logicas is
port(
a, b : in std_logic;
F,F2, F3, F4,F5,F6,F7: out std_logic
);
end Compuertas_logicas;
architecture correr of Compuertas_logicas is
begin
F <= NOT a; -- Compuerta NOT
F2 <= NOT b; -- Compuerta NOT
F3 <= a NAND b; -- Compuerta NAND
F4 <= a NOR b; -- Compuerta NOR
F5 <= a AND b; -- Compuerta AND
F6 <= a OR b; -- Compuerta OR
F7 <= a XOR b; -- Compuerta XOR
end correr;
---------------------------------------------------------------------------------------------
-- Code your testbench here
library IEEE;
use IEEE.std_logic_1164.all;
entity testbench is
end testbench;
architecture tb of testbench is
component Compuertas_logicas is
port(
a: in std_logic;
b: in std_logic;
F: out std_logic;
F2: out std_logic;
F3: out std_logic;
F4: out std_logic;
F5: out std_logic;
F6: out std_logic;
F7: out std_logic
);
end component;
signal a_in, b_in, F_out, F2_out, F3_out, F4_out, F5_out, F6_out, F7_out: std_logic;
begin
-- Connect DUT
DUT: Compuertas_logicas port map(a_in, b_in, F_out, F2_out, F3_out, F4_out, F5_out, F6_out, F7_out);
process
begin
a_in <= '0';
wait for 1 ns;
assert(F_out='1') report "Fail 0/1" severity error;
a_in <= '1';
wait for 1 ns;
assert(F_out='0') report "Fail 1/1" severity error;
b_in <= '1';
wait for 1 ns;
assert(F2_out='0') report "Fail 1/0" severity error;
b_in <= '0';
wait for 1 ns;
assert(F2_out='1') report "Fail 1/1" severity error;
a_in <= '0';
b_in <= '0';
wait for 1 ns;
assert(F3_out='0') report "Fail 0/0" severity error;
a_in <= '1';
b_in <= '0';
wait for 1 ns;
assert(F3_out='1') report "Fail 1/0" severity error;
a_in <= '0';
b_in <= '1';
wait for 1 ns;
assert(F3_out='1') report "Fail 0/1" severity error;
a_in <= '1';
b_in <= '1';
wait for 1 ns;
assert(F3_out='0') report "Fail 1/1" severity error;
a_in <= '0';
b_in <= '0';
wait for 1 ns;
assert(F4_out='1') report "Fail 0/0" severity error;
a_in <= '1';
b_in <= '0';
wait for 1 ns;
assert(F4_out='0') report "Fail 1/0" severity error;
a_in <= '0';
b_in <= '1';
wait for 1 ns;
assert(F4_out='0') report "Fail 0/1" severity error;
a_in <= '1';
b_in <= '1';
wait for 1 ns;
assert(F4_out='0') report "Fail 1/1" severity error;
a_in <= '0';
b_in <= '0';
wait for 1 ns;
assert(F5_out='0') report "Fail 0/0" severity error;
a_in <= '1';
b_in <= '0';
wait for 1 ns;
assert(F5_out='0') report "Fail 1/0" severity error;
a_in <= '0';
b_in <= '1';
wait for 1 ns;
assert(F5_out='0') report "Fail 0/1" severity error;
a_in <= '1';
b_in <= '1';
wait for 1 ns;
assert(F5_out='1') report "Fail 1/1" severity error;
a_in <= '0';
b_in <= '0';
wait for 1 ns;
assert(F6_out='0') report "Fail 0/0" severity error;
a_in <= '1';
b_in <= '0';
wait for 1 ns;
assert(F6_out='1') report "Fail 1/0" severity error;
a_in <= '0';
b_in <= '1';
wait for 1 ns;
assert(F6_out='1') report "Fail 0/1" severity error;
a_in <= '1';
b_in <= '1';
wait for 1 ns;
assert(F6_out='1') report "Fail 1/1" severity error;
a_in <= '0';
b_in <= '0';
wait for 1 ns;
assert(F7_out='0') report "Fail 0/0" severity error;
a_in <= '1';
b_in <= '0';
wait for 1 ns;
assert(F7_out='1') report "Fail 1/0" severity error;
a_in <= '0';
b_in <= '1';
wait for 1 ns;
assert(F7_out='1') report "Fail 0/1" severity error;
a_in <= '1';
b_in <= '1';
wait for 1 ns;
assert(F7_out='0') report "Fail 1/1" severity error;
-- Clear inputs
a_in <= '0';
b_in <= '0';
assert false report "Test done." severity note;
wait;
end process;
end tb;
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