LCD código
para el desarrollo de esta practica fue necesario descargar dos librerías del la pagina de intesc
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE WORK.COMANDOS_LCD_REVD.ALL;
entity LIB_LCD_INTESC_REVD is
GENERIC(
FPGA_CLK : INTEGER := 100_000_000
);
PORT(CLK: IN STD_LOGIC;
-----------------------------------------------------
------------------PUERTOS DE LA LCD------------------
RS : OUT STD_LOGIC; --
RW : OUT STD_LOGIC; --
ENA : OUT STD_LOGIC; --
DATA_LCD : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) --
-----------------------------------------------------
-----------------------------------------------------
-----------------------------------------------------------
--------------ABAJO ESCRIBE TUS PUERTOS--------------------
-----------------------------------------------------------
-----------------------------------------------------------
);
end LIB_LCD_INTESC_REVD;
architecture Behavioral of LIB_LCD_INTESC_REVD is
CONSTANT NUM_INSTRUCCIONES : INTEGER := 16; --INDICAR EL NÚMERO DE INSTRUCCIONES PARA LA LCD
--------------------------------------------------------------------------------
-------------------------SEÑALES DE LA LCD (NO BORRAR)--------------------------
--
component PROCESADOR_LCD_REVD is --
--
GENERIC( --
FPGA_CLK : INTEGER := 50_000_000; --
NUM_INST : INTEGER := 1 --
); --
--
PORT( CLK : IN STD_LOGIC; --
VECTOR_MEM : IN STD_LOGIC_VECTOR(8 DOWNTO 0); --
C1A,C2A,C3A,C4A : IN STD_LOGIC_VECTOR(39 DOWNTO 0); --
C5A,C6A,C7A,C8A : IN STD_LOGIC_VECTOR(39 DOWNTO 0); --
RS : OUT STD_LOGIC; --
RW : OUT STD_LOGIC; --
ENA : OUT STD_LOGIC; --
BD_LCD : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --
DATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --
DIR_MEM : OUT INTEGER RANGE 0 TO NUM_INSTRUCCIONES --
); --
--
end component PROCESADOR_LCD_REVD; --
--
COMPONENT CARACTERES_ESPECIALES_REVD is --
--
PORT( C1,C2,C3,C4 : OUT STD_LOGIC_VECTOR(39 DOWNTO 0); --
C5,C6,C7,C8 : OUT STD_LOGIC_VECTOR(39 DOWNTO 0) --
); --
--
end COMPONENT CARACTERES_ESPECIALES_REVD; --
--
CONSTANT CHAR1 : INTEGER := 1; --
CONSTANT CHAR2 : INTEGER := 2; --
CONSTANT CHAR3 : INTEGER := 3; --
CONSTANT CHAR4 : INTEGER := 4; --
CONSTANT CHAR5 : INTEGER := 5; --
CONSTANT CHAR6 : INTEGER := 6; --
CONSTANT CHAR7 : INTEGER := 7; --
CONSTANT CHAR8 : INTEGER := 8; --
--
type ram is array (0 to NUM_INSTRUCCIONES) of std_logic_vector(8 downto 0); --
signal INST : ram := (others => (others => '0')); --
--
signal blcd : std_logic_vector(7 downto 0):= (others => '0'); --
signal vector_mem : STD_LOGIC_VECTOR(8 DOWNTO 0) := (others => '0'); --
signal c1s,c2s,c3s,c4s : std_logic_vector(39 downto 0) := (others => '0'); --
signal c5s,c6s,c7s,c8s : std_logic_vector(39 downto 0) := (others => '0'); --
signal dir_mem : integer range 0 to NUM_INSTRUCCIONES := 0; --
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
---------------------------AGREGA TUS SEÑALES AQUÍ------------------------------
CONSTANT DELAY_FIN : INTEGER := 24_999_999;
SIGNAL CONTA_DELAY : INTEGER RANGE 0 TO DELAY_FIN := 0;
SIGNAL UNIDADES, DECENAS : INTEGER RANGE 0 TO 9 := 0;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
begin
---------------------------------------------------------------
-------------------COMPONENTES PARA LCD------------------------
--
u1: PROCESADOR_LCD_REVD --
GENERIC map( FPGA_CLK => FPGA_CLK, --
NUM_INST => NUM_INSTRUCCIONES ) --
--
PORT map( CLK,VECTOR_MEM,C1S,C2S,C3S,C4S,C5S,C6S,C7S,C8S,RS, --
RW,ENA,BLCD,DATA_LCD, DIR_MEM ); --
--
U2 : CARACTERES_ESPECIALES_REVD --
PORT MAP( C1S,C2S,C3S,C4S,C5S,C6S,C7S,C8S ); --
--
VECTOR_MEM <= INST(DIR_MEM); --
--
---------------------------------------------------------------
---------------------------------------------------------------
-------------------------------------------------------------------
---------------ESCRIBE TU CÓDIGO PARA LA LCD-----------------------
INST(0) <= LCD_INI("00");
INST(1) <= CHAR(MC);
INST(2) <= CHAR(O);
INST(3) <= CHAR(N);
INST(4) <= CHAR(T);
INST(5) <= CHAR(A);
INST(6) <= CHAR(D);
INST(7) <= CHAR(O);
INST(8) <= CHAR(R);
INST(9) <= CHAR_ASCII(x"3A");
INST(10) <= BUCLE_INI(1);
INST(11) <= POS(2,4);
INST(12) <= INT_NUM(DECENAS);
INST(13) <= POS(2,5);
INST(14) <= INT_NUM(UNIDADES);
INST(15) <= BUCLE_FIN(1);
INST(16) <= CODIGO_FIN(1);
-------------------------------------------------------------------
-------------------------------------------------------------------
-------------------------------------------------------------------
--------------------ESCRIBE TU CÓDIGO DE VHDL----------------------
PROCESS(CLK)
BEGIN
IF RISING_EDGE(CLK) THEN
CONTA_DELAY <= CONTA_DELAY +1;
IF CONTA_DELAY = DELAY_FIN THEN
CONTA_DELAY <= 0;
UNIDADES <= UNIDADES +1;
IF UNIDADES = 9 THEN
UNIDADES <= 0;
DECENAS <= DECENAS +1;
IF DECENAS = 9 THEN
DECENAS <= 0;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-------------------------------------------------------------------
-------------------------------------------------------------------
end Behavioral;
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